I. Field of the Invention
This invention relates generally to communication between two computer processors. More particularly, the present invention relates to an apparatus and method for multidirectional communication between processing devices, in which data is transmitted via a low pin count bus.
II. Background Information
Modern computers may often utilize more than one processor. In addition, a main processor may be used in combination with a number of coprocessors. Coprocessors perform numerous tasks which a processor may perform but which are more efficiently performed by a dedicated device designed for a particular task. Tasks coprocessors perform may include math functions, image or graphics processing functions, audio functions, encryption, and password or identification verification. Often the multiple processors and coprocessors in a computer system are not fabricated on the same chip or located in the same package. However, such devices must communicate with each other, transferring data between them. Furthermore, other devices in a computer system, such as memory devices or I/O devices must communicate with each other and with processors and coprocessors. When used herein, data may include operands, instructions, commands, or any other information, such as text, images, etc.
Typically, devices in a computer system communicate using busses. A bus is a set of one or more lines connecting two or more devices and allowing them to communicate data. Typically, a bus has a protocol which each device connected to the bus must obey. A protocol controls the timing and sequence of data and control signals on a bus. A protocol allows for flow controlxe2x80x94identifying the source and recipient of data sent on the bus, identifying the data itself, and indicating that devices are ready or not ready to send and receive data. Often one device at a time is allowed to transmit data on the bus. Furthermore, often one device at a time is permitted to control the bus, determine which devices transmit data, and determine which data is transmitted; this device is often termed the xe2x80x9cmasterxe2x80x9d device. A protocol also allows for arbitration to determine which device is the master device, particularly when more than one device wishes to transmit data on the bus. A protocol may also provide error detection and correction, and other functions.
To minimize the cost of the bus, the bus needs to be narrowxe2x80x94i.e., to have a low pin count or number of wires. However, it is also desirable to have a bus with a high bandwidth or throughput. Furthermore, it is desirable for a bus to have a high bus efficiency, the ratio of the number of clocks of data sent to the number of clocks required to send the data. These requirements of low pin count on the one hand and high bandwidth and bus efficiency on the other are at odds with each other; known systems having low pin count have low bandwidth and low bus efficiency, and known systems having high bandwidth and high bus efficiency have high pin count. Lowering the pin count on a bus may cause latency overhead, i.e., transmission delays. Reducing the number of lines on a bus may require that data transmission and flow control or arbitration take place on the same line or lines; thus data transmission and flow control or arbitration cannot take place simultaneously, delaying both data transmission and control signals. Such systems may have high buffering overhead, because the lack of flow control during data packet transmission requires receiving devices to maintain large buffers.
Often two devices communicating using a bus may wish to transmit flow control (i.e., not ready to receive) or arbitration (i.e., a bus ownership request) information to each other simultaneously; this may not be possible if the number of control lines for the bus is reduced to one. Typically, more than one device cannot transmit information on the same bus line at the same time. With wider busses, multiple lines are used to allow bus arbitration and flow control to take place during data transmissionxe2x80x94for instance, dedicated bus request and grant lines are used.
Therefore it is desirable to have a bus that is narrow and at the same time has a high bandwidth and high efficiency. It is desirable to have a bus capable of transmitting data and flow control, arbitration and other control signals at the same time. It is desirable to have flow control, arbitration and other control signals take place on a minimum number of lines without incurring the delays associated with such systems.
A method and system are disclosed allowing devices to communicate using a highly efficient low pin count bus comprising a set of data lines, a strobe line, and one control line. Command information is transmitted simultaneously with data, the command information being defined by its timing.